(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of integrating high voltage device fabrication with low voltage salicide processes in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, logic products are often produced using salicide (self-aligned silicide) processes in order to obtain higher circuit performance. In silicidation, a refractory metal layer is deposited and then annealed. The underlying silicon reacts with the refractory metal layer to produce a silicide overlying the gate electrode and source and drain regions. The silicided gate and source/drain regions have lower resistance than non-silicided regions, especially in smaller geometries, and hence, higher circuit performance.
With the advent of Large Scale Integration (LSI), many of the integrated circuits formed on semiconductor substrates comprise several circuit functions on a single chip. For example, memory devices are formed on the same chip as the logic circuits which address them. High voltage devices are required to program or erase a non-volatile memory cell. However, the polysilicon thickness in the salicide process is not enough to resist the high energy ion implant required for a high voltage device. Logic devices and memory devices can have both high and low voltage devices. It is desired to find a method of integrating the salicide process with the fabrication of high voltage devices on one wafer so that high performance of both low voltage devices and high voltage devices can be achieved.
U.S. Pat. No. 5,512,503 to Hong discloses a split gate EEPROM device. U.S. Pat. Nos. 5,482,888 to Hsu et al, 5,721,170 to Bergemont, and 5,776,811 to Wang et al teach various methods of forming high voltage devices. Co-pending U.S. patent application Ser. No. 08/998,630 to J. M. Huang et al, filed on Dec. 29, 1997 teaches a method of integrating salicide and self-aligned contact processes in the fabrication of logic circuits with embedded memory.